1. Technical Field
The present invention relates to a device for providing an interface between a host apparatus and a removable externally connected apparatus.
2. Background Art
There has been available a removable IC memory device known as “memory card”.
The memory card incorporates a nonvolatile semiconductor memory (IC memory) and can store various digital data including still picture data, moving picture data, audio data, music data, etc. The memory card is usable as an external storage medium with a host apparatus such as a portable digital assistant, desk-top computer, notebook computer, mobile phone, audio apparatus, home electric appliances or the like.
Some conventional memory cards use, for data transfer to and from a host apparatus, a three-wire half-duplex serial protocol intended for transfer of three signals including a 1-bit serial data, clock signal and bust-state signal.
The serial data signal is data signal for transfer between a memory card and host apparatus and memory card. The serial data signal varies in transfer direction and attribute thereof according to a statement defined by the bus-state signal.
The bus-state signal is a signal for defining the state of the serial data signal and a timing of starting the transfer of a serial data signal in each state.
The clock signal is a clock for the serial data and bus-state signals to be transferred over a bus. It is transferred from the host apparatus to the memory card. A clock signal is outputted whenever a packet communication which will be described in detail later is in any of three states (BS1 to BS3).
Typical memory cards adopting the above-mentioned three-wire half-duplex serial protocol are known from the disclosures in the Applicant's Japanese Unexamined Application Publication No. 53306 of 1999 and U.S. Pat. No. 6,253,259.
The memory cards disclosed in the above references will be described herebelow as conventional memory cards.
FIG. 1 shows the conventional memory card in the form of a schematic plan view and the terminal block of the memory card in an enlarged scale. As in the plan view in FIG. 1, the conventional memory card is indicated with a reference 500. It is formed like a card having a terminal block including ten terminals or pins 1 to 10.
The pins 1 and 10 are ground (VSS) terminals. The pin 2 is a BS terminal for reception of a bus-state signal from a host apparatus. The pins 3 and 9 are source voltage (VCC) terminals. The pin 4 is an input/output (SDIO) terminal for a serial data signal which is transferred between the memory card and host apparatus. The pins 5 and 7 are auxiliary (reserved) terminals. The pin 6 is a card detection (INS) terminal of which the existence is detected by the host apparatus to determine whether the memory card is inserted in the card slot or not. The pin 8 is a clock (SCLK) terminal reception of a clock signal from the host apparatus.
FIG. 2 shows an example construction of a front-end device of an interface between a conventional memory card 500 and a host apparatus 600.
As shown, the conventional memory card 500 includes a data input buffer 501R, data output buffer 501S, BS input buffer 505 and a CLK input buffer 506.
The above data input buffer 501R and data output buffer 501S are provided as an input/output driver for the SDIO terminal. Also, the BS input buffer 505 is provided as an input driver for the BS terminal. Further, the CLK input buffer 506 is provided as an input driver for the SCLK terminal.
Note here that the data output buffer 501S is a so-called tri-state buffer. In the memory card, since it makes a two-way data communication on one line, so the output driver not used has to be at a high impedance at the output thereof for the memory card to be supplied with data. Thus, the tri-state buffer is used as the data output buffer 501S working as a data output driver. The data output buffer 501S is supplied with an enable signal DE2, as a control signal, from a controller or the like (not shown). When the enable signal DE2 is High, the data output buffer 501S will have a high impedance at the output thereof. On the contrary, when the enable signal DE2 is Low, the data output buffer 501S will have the output thereof enabled.
The memory card 500 further includes a data input flip-flop 511R, data output flip-flop 511S and a BS input flip-flop 515.
The data input flip-flop 511R and data output flip-flop 511S are provided as a latch circuit for input/output data at the SDIO terminal. The BS input flip-flop 515 is provided as a latch circuit for input data at the BS terminal.
The data input flip-flop 511R is supplied with data from the data input buffer 501R and outputs data to the controller or the like (not shown). The data output flip-flop 511S is supplied with data from the controller or the like (not shown) and outputs data to the data output buffer 501S. The BS input flip-flop 515 is supplied with data from the BS input buffer 505 and outputs data to the controller or the like (not shown).
Also, each of the above flip-flops is supplied with a clock signal from the SCLK terminal.
Note here that each of the data input flip-flop 511R and BS input flip-flop 515 latches data synchronously with a timing of the leading edge of the clock signal. On the other hand, the data output flip-flop 511S latches data synchronously with a timing of the trailing edge of the clock signal.
The host apparatus 600 includes a data input buffer 601R, data output buffer 601S, BS output buffer 605 and a CLK output buffer 606.
The data input buffer 601R and data output buffer 601S are provided as an input/output driver for the SDIO terminal. The BS output buffer 605 is provided as an output driver for the BS terminal. The CLK output buffer 606 is provided as an output driver for the SCLK terminal.
Note that the data output buffer 601S is a so-called tri-state buffer. The reason why the data output buffer 601S is a tri-state buffer is similar to that for which the data output buffer 601S in the memory card is a tri-state buffer. The data output buffer 601S is supplied with an enable signal DE1, as a control signal.
When the enable signal DE1 is High, the data output buffer 601S will have a high impedance at the output thereof. On the contrary, when the enable signal DE1 is Low, the data output buffer 601S will have the output thereof enabled. The enable signal DE1 is supplied from the controller or the like (not shown).
The host apparatus 600 further includes a data input flip-flop 611R, data output flip-flop 611S, BS output flip-flop 615 and a clock generator 616.
The data input flip-flop 611R and data output flip-flop 611S are provided as a latch circuit for input/output data at the SDIO terminal. The BS output flip-flop 615 is provided as a latch circuit for output data at the BS terminal.
The clock generator 616 generates a clock signal having a predetermined frequency (20 MHz at maximum, for example).
The data input flip-flop 611R is supplied with data from the data input buffer 601R and outputs data to the controller or the like (not shown). The data output flip-flop 611S is supplied with data from the controller or the like (not shown) and outputs data to the data output buffer 601S. The BS output flip-flop 615 is supplied with data from the controller or the like (not shown) and outputs data to the BS output buffer 605.
Also, each of the above flip-flops is supplied with a clock signal from the clock generator 616.
Note here that each of the data input flip-flop 611R, data output flip-flop 611S and BS output flip-flop 615 latches data synchronously with a timing of the trailing edge of the clock signal.
The front-end circuit constructed as above operates to transmit data from the host apparatus 600 to the memory card 500 as will be described below.
First, the enable signal DE1 in the host apparatus 600 is Low while the enable signal DE2 in the memory card 500 is High. In this case, the host-side data output buffer 601S has the output thereof enabled while the card-side data output buffer 501S has a high impedance at the output thereof. Thus, the serial data (SDIO) will be transmitted from the host apparatus 600 to the memory card 500.
The serial data signal is outputted from the host-side data output flip-flop 611S synchronously with the trailing edge of the clock signal. The serial data signal output from the data output flip-flop 611S is supplied to the card-side data input flip-flop 511R via the data output buffer 601S, pin 4 and data input buffer 501R. The serial data signal is supplied to the card-side data input flip-flop 511R synchronously with the leading edge of the clock signal.
Next, the data transmission from the memory card 500 to the host apparatus 600 will be described.
First, the enable signal DE1 in the host apparatus 600 is High while the enable signal DE2 in the memory card 500 is Low. In this case, the host-side data output buffer 601S has a high impedance at the output thereof while the card-side data output buffer 501S has the output thereof enabled. Thus, the serial data (SDIO) will be transmitted from the memory card 500 to the host apparatus 600.
The serial data signal is outputted from the card-side data output flip-flop 511S synchronously with the trailing edge of the clock signal. The serial data signal output from the data output flip-flop 511S is supplied to the host-side data input flip-flop 611R via the data output buffer 501S, pin 4 and data input buffer 601R. The serial data signal is supplied to the host-side data input flip-flop 611R synchronously with the leading edge of the clock signal.
Note that the bus-state signal is transmitted from the host apparatus 600 to the memory card 500. That is, in this interface, the host apparatus 600 will have the initiative of the data communication.
The bus-state signal is outputted from the host-side BS output flip-flop 615 synchronously with the trailing edge of the clock signal. The bus-state signal output from the BS output flip-flop 615 is supplied to the card-side input flip-flop 515 via the BS output buffer 605, pin 2 and BS input buffer 505. The bus-state signal is supplied to the card-side BS input flip-flip 515 synchronously with the leading edge of the clock signal.
The above clock signal is generated by the clock generator 616 and supplied to each of the flip-flops in the host apparatus 600. Also, the clock signal is supplied to each of the flip-flops in the memory card 500 via the CLK output buffer 606, pin 8 and CLK input buffer 506.
Next, the content of communication by the convention memory card will be described.
In the interface of the conventional memory card, the attribute and direction of the serial data signal are defined by switching the bus-state signal. The state includes four categories: BS0 being a state in which no packet communication is done and BS1 to BS3 in which a packet communication is done. The bus-state signal has the state thereof sequentially switched from BS0 to BS3 by selection of a signal level between High and Low.
Also, the attribute and direction of data in each of the states vary between a read protocol intended for data transfer from the memory card to the host apparatus and a write protocol for data transfer from the host apparatus to the memory card. Also, in the interface of the conventional memory card, the states BS1 to BS3 are taken as one packet for management of the data transmission. That is, the data transfer from the host apparatus to the memory card is managed as “write packet” and that from the memory card to the host apparatus is managed as “read packet”.
The content of communication in each state will be detailed below.
FIG. 3 shows the content of write-packet communication, and FIG. 4 shows the content of read-packet communication.
The state BS0 is a state in which an interrupt (INT) signal can be transferred from the memory card to the host apparatus.
The BS1 is a state in which a TPC (transfer protocol command) command is transferred. The TPC command is a control command transferred from the host apparatus to the memory card.
In the data communication in the state BS2 or BS3, the attribute of serial data signal varies between the read and write packets.
In the data communication in the state BS2, a busy (BSY) signal and ready signal are transferred from the memory card to the host apparatus. More specifically, in the data communication in this state BS2, the busy signal is sent from the memory card to the host apparatus when the memory card is not ready for any data transfer. When the memory card is ready for the data transfer, the ready signal is sent from the memory card to the host apparatus.
In the data communication in the state BS2, data to be written is transferred from the host apparatus to the memory card according to the write protocol.
In the data communication in the state BS3, data to be read is transferred from the memory card to the host apparatus according to the read protocol.
In the data communication in the state BS3, the busy and ready signals are transferred from the memory card to the host apparatus according to write protocol. In this data communication in the state BS3, when the procedure for data transfer from the host apparatus to the memory card is not complete, the busy signal is sent from the memory card. When the procedure is complete, the ready signal is sent from the memory card.
Note here that the aforementioned conventional memory card makes a serial transmission with a transfer clock of 20 MHz at maximum. Therefore, the maximum data transfer rate is 20 Mbps. Recently, however, the flash memory used in the memory card has an increased capacity and a higher write/read speed. In this circumstance, a memory card is demanded which has a higher data transfer rate.
Further, the memory card demanded to have a higher data transfer rate as above should be interchangeable with the conventional memory card.
Also, the conventional memory card should be able to detect a bus-state signal transferred from the host apparatus synchronously with the leading edge of a clock signal and send data synchronously with the trailing edge of the clock signal as above.
For the above purpose, the conventional memory card should be able to detect switching of the bus-state signal at the leading edge (T101) of the clock signal and start sending data at a trailing edge (T102) next to the leading edge as shown in FIG. 5, for example. Thus, an operation responsive to the BS switching has to be done in a half period of the clock signal. Therefore, in the conventional memory card, the data transfer rate depends upon a time (25 nsec at minimum) being a half of the period of the clock signal, not upon the actual period (50 nsec at maximum) of the clock signal, which will restrict the increase of the data transfer rate.
Also, in the conventional memory card, since one data line is used in the two-way data communication, so a state is defined by a bus-state signal to determine a direction of data transmission. Thus, the direction of data transfer is switched according to the switching of the bus-state signal. For example, when the state is switched from BS0 to BS1 and from BS2 to BS3 in the write-packet communication or when the state is switched from BS0 to BS1 and from BS1 to BS2 in the read-packet communication, the direction of data transfer is switched.
In the conventional memory card, the host-side enable signal DE1 and card-side enable signal DE2 are changed in level in response to the switching of the bus-state signal to accommodate the switched data transfer direction.
However, the signal level has to be changed synchronously with the first trailing edge after the bus-state signal is sent. Thus, the host-side enable signal DE1 and card-side enable signal DE2 are changed in level nearly at the same time. Thus, when either of the enable signals is changed not synchronously with the trailing edge with the results of the enable signal DE1 being Low in level and the enable signal DE2 being Low, for example, that is to say, when both the host-side and card-side output drivers are enabled, the data buses will conflict with each other. To avoid such a conflict between the data buses, the conventional memory card has to be designed for the enable signals DE1 and DE2 to be changed strictly synchronously with the trailing signal of the clocks signal.